si_fab.all.M1M2ViaWireTraceTemplate

class si_fab.all.M1M2ViaWireTraceTemplate

Electrical wire template to connect the M1 and M2 metal layers with a via.

Parameters:

pitch:

name: String that contains only ISO/IEC 8859-1 (extended ASCII py3) or pure ASCII (py2) characters

The unique name of the pcell

Layout

Parameters

windows: List with type restriction, allowed types: <class ‘ipkiss3.pcell.trace.window.window._TraceWindow’>

List of Trace Windows that know how to draw themselves relative to the shape of the Trace

layer: __Layer__

pin_shape: Shape

shape to be used for the pins

trace_template_for_ports: _TraceTemplate.Layout

Trace template to be used for the ports. Default = this template

control_shape_layer: __Layer__

layer on which the control shape is drawn

draw_control_shape: ( bool, bool_ or int )

draws the control shape on top of the waveguide

width: float and number > 0

Width of the electrical trace

view_name: String that contains only alphanumeric characters from the ASCII set or contains _$. ASCII set is extended on PY3.

The name of the view