NetlistExtractionSettings

class ipkiss3.all.NetlistExtractionSettings

Configuration settings for extracting a netlist from a layout.

These settings are used in i3.NetlistFromLayout and to_canvas.

• In NetlistFromLayout, electrical is False by default.

• In to_canvas, electrical is True by default.

IPKISS can extract both optical and electrical netlists.

Optical netlist extraction

There are no configuration options for optical netlist extraction. Ports are considered connected if they are at the same position, with angles facing each other (180 degree difference). In addition trace templates should be the same.

Electrical netlist extraction

Since IPKISS 3.10 it is possible to extract the electrical netlist. The default behavior for the electrical netlist extraction is to directly define a net between two connected electrical devices. For instance, if you use a ConnectElectrical from inst1:m1 to inst2:m1, an ElectricalWire cell (inst3) will be generated in the layout (similar to how ConnectManhattan generates a RoundedWaveguide), but the resulting netlist will not contain inst3. The resulting net is inst1:m1 to inst2:m1.

Limitations

• Full electrical netlist extraction currently assumes the ports’ layer is drawn on an actual metal layer.

  Using a PINREC layer is not yet supported.

• Configuration is not yet part of the TECH tree and hence not enabled by default for foundry PDK.

Parameters:

connected_layers: list, optional

List of tuples of electrical layers that can be considered connected.

electrical: ( bool, bool_ or int ), optional

Whether or not to extract the full electrical netlist. When False, only exposed ports are extracted, when True, also extract nets between instances.

Examples

import si_fab.all as pdk
import ipkiss3.all as i3
from ipkiss3.pcell.layout.netlist_extraction import extract_netlist

class DummyBondpad(i3.PCell):
    trace_template = i3.TraceTemplateProperty()

    def _default_trace_template(self):
        tt = i3.ElectricalWireTemplate()
        tt.Layout(width=10)
        return tt

    class Layout(i3.LayoutView):
        def _generate_elements(self, elems):
            elems += i3.Rectangle(layer=i3.TECH.PPLAYER.M1.LINE, box_size=(50, 50))
            return elems

        def _generate_ports(self, ports):
            ports += i3.ElectricalPort(
                name="in", position=(0, 0), trace_template=self.trace_template, layer=self.trace_template.layer
            )
            return ports

    class Netlist(i3.NetlistFromLayout):
        pass

sample_circuit = i3.Circuit(
    insts={"bp1": DummyBondpad(), "bp2": DummyBondpad()},
    specs=[
        i3.Place("bp1", (0, 0)),
        i3.Place("bp2", (250, 250)),
        i3.ConnectElectrical("bp1:in", "bp2:in", start_angle=0, end_angle=-90),
    ],
    exposed_ports={"bp1:in": "in", "bp2:in": "out"},
)
lv = sample_circuit.get_default_view(i3.LayoutView)
lv.visualize()
nl = extract_netlist(layout_view=lv, settings=i3.NetlistExtractionSettings(electrical=True))
print(nl)

# This will print:

# netlist:
# --------
# instances:
#     - bp1 : <Single instance in netlist of PCELL_1>
#     - bp2 : <Single instance in netlist of PCELL_2>
#
# terms:
#     - in
#     - out
#
# nets:
#     - in-out-bp1:in-bp2:in: <ElectricalNet Net 'in-out-bp1:in-bp2:in' with terms:
#       [<Term Term 'in' on domain ElectricalDomain>,<Term Term 'out' on domain ElectricalDomain>,
#        <InstanceTerm bp1:in>,<InstanceTerm bp2:in>]>