Release notes IPKISS Photonics Design Platform 3.6.0

The IPKISS Photonics Design Platform 3.6 features a new integration with the Eigenmode Expansion (EME) solver of Ansys Lumerical MODE. A lot of improvements and bugfixes were implemented also in IPKISS itself, the Caphe circuit simulator, IPKISS AWG Designer, and the IPKISS Link for Siemens EDA.

A full list of improvements can be found in the changelog.

Highlights are shown below:

Device simulation (IPKISS Link for Ansys Lumerical)

With this release, designers can now use the EME solver of Lumerical MODE to simulate and extract an S-Matrix directly from an IPKISS layout using i3.device_sim.LumericalEMESimulation.

With our device simulation links for Dassault Systèmes Simulia (CST Studio Suite) and Ansys Lumerical, designers can take any device from one of the supported foundries (IPKISS PDKs) or from custom technologies, have them virtually fabricated by IPKISS, define the simulation recipe directly within IPKISS and then run the simulation in one of the supported simulation tools. Simulation results are stored in Touchstone format and can be imported back into the IPKISS framework to build compact models, which can then be used to build circuits consisting of multiple building blocks and run circuit simulations using IPKISS Caphe.

Several macros have been added to the product that allow to finetune your simulation recipes (see Device simulation reference). For example, placing field monitors for visualizing the fields after the simulation (in the CAD tool itself), extracting neff from a mode, and adjusting various simulation settings in EME.

The tutorial to get started with physical simulations (physical device simulation) has been revised and streamlined.

Layout improvements

The placement engine (i3.place_insts) allows to place instances based on electrical ports identifiers. This makes it easier to solve a certain class of placement and routing problems with electrical devices.

For the designers that always wondered where their layout labels were, want to get rid of even more of those pesky DRC errors, and get frustrated at hard-to-control tapered waveguides, we have several bug fixes and improvements for you. See the changelog for a complete list.

AWG Designer

Two drawing improvements have been implemented to ensure DRC-clean AWGs in several technologies:

• Improvements in the star coupler contour

• Improvements in the fanout section from the star coupler

Caphe

Users can now run both a time and frequency domain simulation from the same Python process.

IPKISS Link for Siemens EDA

We have significantly improved the error reporting when a library cannot be loaded, which helps to quickly identify the source.