Design Automation

The design automation glossary starts with common concepts and then dives deeper into specific design actions related terms such as for layout, simulation, verification and file formats.



Integrated Circuit. A circuit consisting of possibly many components on a single chip. A Photonic IC handles both optical and electrical signals on a chip.


The set of data representing an IC or a part of an IC: Layout data, Netlist data, Schematic data and other information.


The drawings representing a Design at the physical level. Combines several aspects of the physical implementation:

  • At least, what is needed to send the Design to the Fab for fabrication, including Drawn data.

  • Optionally, documentation for human or computer inspection and analysis of the Layout.

  • Optionally, data related to Maskprep such as Filler exclusion zones.

  • Optionally, data related to DRC such as DRC exclusion zones.

  • Optionally, data required for LVS such as Devrec and Pinrec drawings.


The data representing the logical composition and interfaces of a Design:

  • Its interfaces (Term).

  • Its subcomponents (Cell Instance).

  • The Net interconnecting its Instances and interconnecting Instances with its Terms.

In IPKISS, the netlist is defined in the NetlistView.


Short for Terminal. Provides the interface of a Cell to the outside world. Part of the Netlist (logical representation).


The physical interface (optical, electrical, ….) of a Cell to the outside world. Part of the Layout (mask drawing representation). Corresponds to a Term in the Netlist.

  • Interconnects Instances with each other.

  • Interconnects Instances with the Terms of the Netlist.


The visual representation of a Design at the the logical level:

  • Visual representation of its Netlist.

  • Optionally, documentation for human or computer inspection of the Schematic.


The Cell is the unit of reuse in design automation. It is a predefined unit which can take multiple forms:

  • It can be a basic functional element, e.g. a waveguide splitter, resistor,… which in itself is not broken up further. (Primitive cell).

  • It can be a layout primitive which is used to avoid drawing the same layout part over and over again, but has no function by itself.

  • It can be composed of other cells, optionally interconnected, thus creating a building block with higher-level functionality (Hierarchical cell).

A Design is created by placing and possibly interconnecting Cells. The same Cell can be used many times, thus avoiding having to draw the same functional element over and over again. As a result, a Design is basically a Cell as well, and could be reused at yet a higher level of design (e.g. the complete chip design could be loaded inside a package design).

Cells are organized in libraries (Library).


A collection of cells (Cell) logically belonging together. For instance, a PDK comes with at least one Library which contains the cells predefined by the Foundry. A designer can maintain his or her own Library of reusable Cells on top of a Foundry PDK, so that work can be reused across design projects.


A collection of properties and data of a Cell relating to a specific part of the design flow. The Layout, Netlist and Schematic are each traditionally matched with a view in each cell. But other views are possible as well, and IPKISS uses for instance views describing specific simulation aspects.

  • Layout View: contains the layout drawings and metadata relating to Layout

  • Netlist View: contains the Cells and the interconnections the Cell is composed of

  • Symbol View: a drawing and metadata which is used to represent the Cell in a Schematic of a higher-level Cell.

  • Schematic View: the graphical representation of a Cell’s Netlist, with additional data for instance for inspection.


The approach taken by most EDA tools to organize data in a Library / Cell / View hierarchy. A Design can use Cells from multiple Libraries. Each Library can have a multitude of Cells, and each Cell can have multiple Views.


Synonym for Cell.


Parametric Cell, a Cell with parameters, which can generate its View data based on those parameters. In IPKISS, every Cell is a PCell, subclassing from i3.PCell.

Primitive cell

A cell which provides a low-level building block which is not composed of other cells. This is also called an atomic cell.

Hierarchical cell

A cell which is composed of instances (Instance) of other cells (Child cell) which can be interconnected. The child cells could be primitive cells or hierarchical cells themselves. Possibly also adds Layout drawings on top of the child cells.

Child cell

A cell which is instantiated in a Hierarchical cell.


A reference to a predefined Cell. By placing instances, in a cell, to already defined cells, a Hierarchical cell is obtained. In IPKISS, instances can be created using reference elements.

Technology File

A file or set of files for a design automation tool which specify the technology aspects such as layers and rules. In some tools, this is one file aka techfile. In IPKISS, it takes the form of a Python package which usually consists of several structured Python modules to make all the information easier to maintain. All the technology-related settings which are needed to tape out to a specific Fab and/or which are necessary for IPKISS to run are implemented in this technology package. Usually, the technology package for IPKISS is part of a larger PDK although also stand-alone technology packages can be used.


An algorithm to connect ports together, taking into account several requirements (e.g. bend radius). An example is i3.RouteManhattan which generates a path between 2 ports ensuring that the sections follow a manhattan direction (north, south, east, west).


Connectors generate a cell to connect two ports with a predefined algorithm, packaging the knowledge to do that into one place (a python class), reusable for many connections. The input is a start and an end port and possibily some parameters. The output is a cell object (usually a Waveguide object).

Semiconductor ecosystem


Shorthand for the fabrication facility manufacturing an IC. Can be in-house (integrated device manufacturer model) or a 3rd party (fabless model).


Near-synonym of Fab: In a fabless model aka foundry model, IC manufacturing is outsourced to an external Fab, called the Foundry. Foundry companies can be pure-play (they only make ICs, not end products) or mixed (they also have a product business like an IDM)


Integrated Device Manufacturer, a company doing everything from design and manufacturing of an IC to the design and manufacturing of an end product. Many IDMs now also outsource parts of their value chain, e.g. for testing or packaging.


Process Design Kit: the set of rules, guidelines, Technology File and predefined cells (Cell) provided by a Fab or Foundry to successfully implement a Design for a specific technology run by that Fab. The PDK is an interface between the designer, the Fab and the design automation software such as IPKISS, and is therefore a key component in the supply chain. Official PDKs supported by IPKISS are listed here.

Design IP

Intellectual property in the form of re-useable circuits and components, validated to some degree in hardware. Can be internal to a design team, such as a library of circuits and components that are used in different products or product versions. Can also be externally sourced from a Design IP supplier that specializes in the creation and validation of re-useable designs. Hard IP comes in the form of layout (GDSII) files that can be included in a larger design. Soft IP comes in the form of code (e.g. VHDL in digital electronics), and is often parameterized to some extent.

Layout and mask

Drawn data

Drawings on the mask drawn by the designer on a Drawn layer in the Layout.

Drawn layer

A layer on which the designer draws, as opposed to a Generated layer. Some drawn layers directly result in a physical mask layer. However, on many layers post-processing will be done by generating new data on the basis of this drawn layer, often in combination with other drawn layers. For instance, the final mask layer might involve executing a boolean operation between multiple drawn layers. Or the empty areas might be filled with Filler structures.

Generated layer

A layer on which the data is generated by the Fab during Maskprep. For instance, a final mask may be generated by subtracting one Drawn layer from another. Or a certain layer might be generated by automatically sizing a Drawn layer.


A non-functional structure which is used to fill empty space on the mask. A Design will always contain empty space between structures. However, some mask layers typically have density requirements. Several key process steps such as lithography, etching and chemo-mechanical polishing are affected by the mask density or the topology of the layer that is being processed. In order to have a controlled density and topology, the empty areas in important mask layer (e.g. waveguide, metal) be often be filled using a repetitive pattern of a ‘filler’ structure. This action is called tiling or dummy filling and is usually performed by the Fab. Also called Dummy or Tile in semiconductor language. We avoid to use the word Dummy since the Dummy is used at Luceda to indicate a matching dummy.

Filler exclusion

A zone on the mask or on a mask layer, indicated by a specific layer, which should not be tiled with Filler structures. This can sometimes be done on small zones in order to avoid interaction between the fillers and functional structures. The layer is typically called NODUM or NOFILL or similar. In some technologies, such exclusion can be specified for specific layers, e.g. M1:NOFILL would avoid filling the indicated areas with M1 tiles, but not on the other layers.


The activity of preparing the mask files for fabrication. This involves final checking and correction of features, executing boolean operations which yield the final mask layers, loading of alignment marks, registration, fab test structures and other required data, and writing of the final files which are sent to the mask shop manufacturing the maskset.


A copy of a functional structure (e.g. transistor, resistor, waveguide, …) located close by the functional structure itself, in order to reduce the effect of certain fabrication variations. This copy is only used for matching and has no function in the circuit itself, hence its name dummy. For instance, in the Luceda AWG Designer, an array of waveguide apertures is usually extended with a few dummy apertures at either side. In this way the outermost functional apertures ‘see’ the same surroundings as the inner apertures. This has an effect on the process, for instance reducing etch bias which the outer apertures might otherwise have compared to the inner apertures, but also may have an effect on the optical behavior since the coupling between apertures can thus be matched. Not to be confused with a non-functional Filler.

User unit

The unit in which the user (of the software) expresses coordinates and dimensions in a layout. Typically 1 micrometer (1e-6). In IPKISS this is set as TECH.METRICS.UNIT


Circuit Model

An approximate model of an (electro-)optical device which describes its behavior. This description can be used to run fast circuit simulations. Also called a behavioral model or compact model (which usually refers to a behavioral model in which physical parameters such as length and width can be tuned). This is explained in circuit model representation.



Layout database file format for exchange of mask layout information. Originally developed by the Calma company for its ‘Graphic Data Sytem’. Although it has limits in scaling for large and complex masksets, and a new format ‘OASIS’ has been developed, GDSII still remains as the de-facto standard for exchange between designers and foundries.


A textual fileformat to store the S-parameters of a component for a given frequency sweep. These S-parameters can come from a simulation or a measurement. IPKISS has functionality to import touchstone files.



The act of applying methods to verify that a Design meets certain constraints.


Design Rule Checking: a thorough check that the Design meets fabrication and manufacturability constraints imposed by the Foundry. The Layout is verified against a set of Design rules defined by the foundry. Examples are minimum width, minimum spacing and overlap rules, avoiding acute angles and so on.

DRC Exclusion

A zone, indicated by a specific layer, in which DRC does not need to be performed. This usually needs specific agreement from the Fab and the designer has to accept that the structures might not be manufacturable.


Layout Versus Schematic: a check of the Layout (physical representation) against the intended Schematic (logical representation). From the Schematic, a netlist is exported. From the Layout, a netlist is extracted using netlist extraction. The two netlists are then compared in order to detect mismatches in Cells or their interconnections.


Device recognition zone. Metadata in the Layout which indicates the edges of a Device. A LVS tool can use the Devrec to extract the devices in the netlist.


Pin recognition zone. Metadata in the Layout which indicates the pins of a Device. A LVS tool can use this to extract the connectivity between devices.