Technology settings
The PDK contains layer definitions and virtual fabrication settings. Refer to the Germanium-on-Silicon design rule manual.
Layers
The following table gives an overview of the available layers and how they are named in IPKISS. See the Germanium-on-Silicon design rules manual for further information about the layers defined by cornerstone_ge_on_si.
Layer Name |
Purpose Name |
Description |
IPKISS Name (TECH.PPLAYER) |
GDSII Layer/Type |
|---|---|---|---|---|
Bleed |
DRAWING |
35-um-wide area at the edges of the design area for dicing streets. |
Bleed |
98/0 |
DevRec |
DRAWING |
Device recognition layer |
DevRec |
68/0 |
FbrTgt |
DRAWING |
Fiber ports on grating couplers (Fiber Target) |
FbrTgt |
81/0 |
FinalChipSize |
DRAWING |
Layer for indicating the Size of chip after dicing (size in x and y). |
FinalChipSize |
99/1 |
Floorplan |
DRAWING |
Cell outline |
Floorplan |
99/0 |
Ge_Etch1_DF |
DRAWING |
1.8 um+-200nm Ge etch to define rib waveguides. Layer will be etched. |
Ge_Etch1_DF |
304/0 |
Ge_Etch1_LF |
DRAWING |
1.8 um+-200nm Ge etch to define rib waveguides. Layer will be protected. |
Ge_Etch1_LF |
303/0 |
Label |
DRAWING |
Labels (dark) |
Label |
100/0 |
None |
DRAWING |
No specific process |
None |
|
PinRec |
DRAWING |
Optical port (pin) recognition layer |
PinRec |
1/10 |
PinRecM |
DRAWING |
Electrical port recognition layer |
PinRecM |
1/11 |
Text |
DRAWING |
Text layer |
Text |
66/0 |